[verilog] counter 구현

counter.v 파일

`timescale 1ns/1ns
module counter (rst, on, clk, count, in, out0609);

input rst, on, clk;
output reg [3:0] count;


reg [6:0]tmp;

input in;
output reg [6:0] out0609;

always@(posedge clk) begin

	
	if(rst == 0) begin
		count = 0;
		out0609 = 0;
	end
	
	else if (on) begin	//on이 1일때 가동
		if(count == 6) begin
			count <=0;
			
			out0609 <= tmp;
			tmp <= 0;
		end
			
		else begin
			count <= count + 1;	
			tmp[count] <= in;
			
		end
	end
end
	
endmodule

 

counter_tb.v 파일

`timescale 1ns/1ns



module counter_tb();

parameter [83:0] pj1data = 84'b100100011001011101100110110011011111011111101011111011111110010110110011001000101011;
parameter pj1legth = 84;

	reg rst, on, clk;
	wire [3:0] count;
	
	reg in;
	wire [6:0] out0609;
	
	reg [83:0] data;
	integer i;
	
	counter u1 (rst, on, clk, count, in, out0609);

	
	initial begin
		rst = 0; on = 1; clk = 0; in = 0;
		data = pj1data;
		
		#4 rst = 1;
		//#2 on = 1;s
		
		if (clk ==1) begin
			for (i=pj1legth-1; i>=0 ; i=i-1)
			 in = data[i]; 
		end
		else in = in;
		
		
		
		#50 $finish; 
	
	end
	
	always begin 
		#1 clk <= ~clk; 
	end
	

initial begin
	
	$dumpfile("output.vcd");
	$dumpvars(0);
	$monitor("count:%d,  out0609:%b", count, out0609);
end

endmodule