목록verilog#counter (1)

from palette import colorful_colors

[verilog] counter 구현

counter.v 파일 `timescale 1ns/1ns module counter (rst, on, clk, count, in, out0609); input rst, on, clk; output reg [3:0] count; reg [6:0]tmp; input in; output reg [6:0] out0609; always@(posedge clk) begin if(rst == 0) begin count = 0; out0609 = 0; end else if (on) begin//on이 1일때 가동 if(count == 6) begin count
EE 학부과목/verilog 2023. 3. 13. 14:45
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