목록verilog#nand (1)

from palette import colorful_colors

[verilog] NAND 구현

nand.vmodule NANDgate(in1, in2, out1); input in1; input in2; output out1; assign out1 = ~(in1 & in2); endmodule nand_tb.v`timescale 1ns/1ns module NANDgate_tb(); reg a; reg b; wire out1; NANDgate u1 (a, b,out1); initial begin a = 0 ; b = 0 ; #100 $finish; end always begin #5 a = ~a; end always begin #10 b = ~b; end /* 위 always문 이용 대신 initial문 안에 a = 0; b = 0 #5; a = 1; b = 0 #5; a = 0; b = 1 #5;..
EE 학부과목/verilog 2023. 3. 13. 12:02
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